DACs are used in an increasing number of applications, many requiring lower power consumption and higher operating frequencies. Direct Digital Synthesis (DDS) is one of these applications. Basic DDS circuits include an electronic controller, random access memory, a frequency reference, a counter, and a DAC. Some versions of DDS circuits include random access memory (RAM).
Multiplying-Adding
Within direct digital synthesizer circuits, improved spurious free dynamic range (SFDR) is desired. One method to achieve improved SFDR is by adding interpolation to the output of the DDS. To determine the interpolation, an approximation of X sin(theta)+Y cos(theta) can be used. This approximation necessitates the need for an efficient method of multiplication in order to preserve high speed operation of the DDS and minimize power consumption. The traditional method of multiplying two binary numbers involves the use of digital adder circuitry. Digital adder circuitry increases the power consumption of the circuit and reduces operating speed.
The following explanatory discussion involves quotients A and B. A is a 3-bit binary number and B is a 2-bit binary number. The notation for the expanded version of A is A2 A1 A0 and the notation for the expanded version of B is B1 B0. The use of the specific bit-widths is convenient for illustration and implementation, but any bit-widths could be used.
In a traditional binary multiplier approach, each bit of the multiplier is multiplied against the multiplicand and positioned according to the position of the bit within the multiplier, and the resulting products are then summed to form the final result.
Using A and B, this would be:
                                                                        S                ⁢                                                                  ⁢                1                            =                                                                                          S                ⁢                                                                  ⁢                2                            =                                          ⁢                                                                                                                                                                                                                                                                                                                                ⁢                                  A                  ⁢                                                                          ⁢                  2                                                                                                                                      ⁢                                  A                  ⁢                                                                          ⁢                  1                                ⁢                                                                                                                                                                        ⁢                                  A                  ⁢                                                                          ⁢                  0                                                                                        ×                                                                                                                                                                                                                                                                                                                    ⁢                                  B                  ⁢                                                                          ⁢                  1                                                                                                                                      ⁢                                  B                  ⁢                                                                          ⁢                  0                                                                                                                                                                                            A                ⁢                                                                  ⁢                                  2                  ·                  B                                ⁢                                                                  ⁢                0                                                                    A                ⁢                                                                  ⁢                                  1                  ·                  B                                ⁢                                                                  ⁢                0                                                                    A                ⁢                                                                  ⁢                                  0                  ·                  B                                ⁢                                                                  ⁢                0                                                                                        A                ⁢                                                                  ⁢                                  2                  ·                  B                                ⁢                                                                  ⁢                1                                                                    A                ⁢                                                                  ⁢                                  1                  ·                  B                                ⁢                                                                  ⁢                1                                                                    A                ⁢                                                                  ⁢                                  0                  ·                  B                                ⁢                                                                  ⁢                1                                                                                                                              }    ⁢  Partial  ⁢          ⁢  Sums
Where the final result of A·B=S1+S2 and the result is a 5-bit binary number that is then fed into a digital to analog converter (DAC) circuit.
FIG. 1 depicts a block diagram 100 of a known multiplication method. As described above, it computes partial sums 105, adds S1 and S2 110 to provide a 5-bit input to 5-bit binary DAC 115. Binary 5-bit DAC 115 has weights of 1, 2, 4, 8, and 16, denoted below by DAC1, DAC2, DAC4, DAC8, and DAC16. The resulting logic equations needed to drive the DAC are:DAC1=A0*B0DAC2=(A1*B0){circle around (+)}(A0*B1)DAC4=((A1·B0)·(A0·B1)){circle around (+)}(A2·B0){circle around (+)}(A1·B1)DAC8=((((A1·B0)·(A0·B1))·((A2·B0)+(A1·B1)))+((A2·B0)+(A1·B1))){circle around (+)}(A2·B1)DAC16=(((((A1·B0)·(A0·B1))·((A2·B0)+(A1·B1)))+((A2·B0)+(A1·B1))·(A2B1)
A large number of gates is involved in the complex logic required to compute this result. This leads to high power consumption and large propagation delay which can decrease speed or necessitate pipelining.
RTZ
The use of return to zero (RTZ) in digital to analog converter (DAC) circuits is a method for doubling the null frequency of sin(x)/x roll-off inherent in DACs. RTZ also helps to reduce switching glitches in the DAC output. Typical approaches return to zero for differential outputs, but return to a rail for single-ended outputs. This introduces a common mode noise signal which can not be totally eliminated in a differential receiver due to practical common mode rejection ratio (CMRR) characteristics. The approach also lends itself to a long worst case slew rate.
In practice, the RTZ is implemented by switching current away from the DAC summing junction.
FIG. 6 is a schematic 600 of the typical known prior art DAC current switch. When NRZ (not return to zero) is high, the current is steered through one of the resistors based on the state of bitp/bitn, so the output voltage at outp/outn is either 0 volts or −I*RV (assuming the top rail is ground, although it could be at any arbitrary voltage). When RTZ is high, the current will not be steered through either resistor, so the both sides of the output are at 0 volts.
FIG. 7 displays a graph 700 of a typical prior art single-ended RTZ DAC output 705 of a sine-wave 710 for the switch of FIG. 6. While the typical RTZ differentially returns to zero, single-endedly it returns to a rail. This approach has a long slew rate when returning to zero from an output at the bottom rail. A true return to zero would return to the midpoint of the DAC output range.
What is needed is a method and apparatus for enhanced DAC performance through improved spurious free dynamic range (SFDR) and accurate return to zero (RTZ) performance.